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| IS61SP6464 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM FEATURES * Fast access time: - 133, 117, 100 MHz; 6 ns (83 MHz); 7 ns (75 MHz); 8 ns (66 MHz) * Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data and control * PentiumTM or linear burst sequence control using MODE input * Five chip enables for simple depth expansion and address pipelining * Common data inputs and data outputs * Power-down control by ZZ input * JEDEC 128-Pin TQFP 14mm x 20mm package * Single +3.3V power supply * Control pins mode upon power-up: - MODE in interleave burst mode - ZZ in normal operation mode These control pins can be connected to GNDQ or VCCQ to alter their power-up state ISSI (R) APRIL 2001 DESCRIPTION The ISSI IS61SP6464 is a high-speed, low-power synchronous static RAM designed to provide a burstable, highperformance, secondary cache for the i486TM, PentiumTM, 680X0TM, and PowerPCTM microprocessors. It is organized as 65,536 words by 64 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to eight bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 controls I/O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49I/O56, BW8 controls I/O57-I/O64, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61SP6464 and controlled by the ADV (burst address advance) input pin. Asynchronous signals include output enable (OE), sleep mode input (ZZ), and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW (or no connect), the SRAM normally operates after the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ (or no connect) on MODE pin selects INTERLEAVED Burst. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 1 IS61SP6464 BLOCK DIAGRAM ISSI MODE Q0 A0' (R) CLK CLK A0 BINARY COUNTER ADV ADSC ADSP CE CLR Q1 A1' A1 64K x 64 MEMORY ARRAY 14 16 A15-A0 16 D Q ADDRESS REGISTER CE CLK 64 64 GW BWE BW8 D Q DQ57-DQ64 BYTE WRITE REGISTERS CLK D BW1 Q DQ8-DQ1 BYTE WRITE REGISTERS CLK CE CE2 CE2 CE3 CE3 D Q 8 ENABLE REGISTER CE CLK INPUT REGISTERS CLK OUTPUT REGISTERS CLK OE 64 DATA[64:1] D Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SP6464 PIN CONFIGURATION 128-Pin TQFP VCCQ CE3 CE2 CE3 CE2 GND VCC CE BW8 BW7 BW6 BW5 OE CLK BWE GW BW4 BW3 GND VCC BW2 BW1 ADSC ADSP ADV GNDQ ISSI (R) 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 GNDQ I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 I/O40 I/O41 I/O42 I/O43 VCCQ GNDQ I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 VCCQ GNDQ I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64 VCCQ PIN DESCRIPTIONS A0-A15 CLK ADSP ADSC ADV BW1-BW8 BWE GW CE, CE2, CE2, CE3, CE3 OE Address Inputs Clock Processor Address Status Controller Address Status Burst Address Advance Synchronous Byte Write Enable Byte Write Enable Global Write Enable Synchronous Chip Enable Output Enable NC GNDQ I/O1-I/O64 ZZ MODE VCC GND VCCQ Data Input/Output Sleep Mode Burst Sequence Mode +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V No Connect Isolated Output Buffer Ground Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 GNDQ NC MODE A15 A14 A13 VCC GND A12 A11 A10 A9 A8 NC A7 A6 A5 A4 A3 VCC GND A2 A1 A0 ZZ VCCQ 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VCCQ I/O32 I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 I/O23 I/O22 GNDQ VCCQ I/O21 I/O20 I/O19 I/O18 I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 GNDQ VCCQ I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 GNDQ 3 IS61SP6464 TRUTH TABLE OPERATION Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst ADDRESS USED CE3 None None None None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current X L X X X L X X X H H H H H X X X X X X X X X X X X CE2 X X L X X X L X X H H H H H X X X X X X X X X X X X CE3 X X X H X X X H X L L L L L X X X X X X X X X X X X CE2 X X X X H X X X H L L L L L X X X X X X X X X X X X CE H L L L L L L L L L L L L L X X H H X H X X H H X H ADSP ADSC ADV WRITE X L L L L H H H H L L H H H H H X X H X H H X X H X L X X X X L L L L X X L L L H H H H H H H H H H H H X X X X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X X X X L H H H H H H L L H H H H L L ISSI OE CLK X X X X X X X X X L H X L H L H L H X X L H L H X X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H I/O (R) High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Dout High-Z Din Dout High-Z Dout High-Z Dout High-Z Din Din Dout High-Z Dout High-Z Din Din Notes: 1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK). 2. Wait states are inserted by suspending burst. 3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW8) and BWE are LOW or GW is LOW. WRITE=H means all byte write enable signals are HIGH. 4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time. 5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock. 4 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SP6464 ASYNCHRONOUS TRUTH TABLE Operation Pipelined Read Pipelined Read Write Write Deselect Sleep ZZ L L L L L H OE ISSI I/O STATUS Dout High-Z High-Z Din High-Z High-Z L H L H X X (R) WRITE TRUTH TABLE Operation Read Read Write all bytes Write all bytes Write Byte 1 Write Byte 2 Write Byte 3 Write Byte 4 Write Byte 5 Write Byte 6 Write Byte 7 Write Byte 8 GW H H H L H H H H H H H H BWE H L L X L L L L L L L L BW8 X H L X H H H H H H H L BW7 X H L X H H H H H H L H BW6 X H L X H H H H H L H H BW5 X H L X H H H H L H H H BW4 X H L X H H H L H H H H BW3 X H L X H H L H H H H H BW2 X H L X H L H H H H H H BW1 X H L X L H H H H H H H INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 5 IS61SP6464 LINEAR BURST ADDRESS TABLE (MODE = GNDQ) ISSI 0,0 (R) A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TBIAS TSTG PD IOUT VIN, VOUT VIN VCC Parameter Temperature Under Bias Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Voltage on Vcc Supply Relatiive to GND Value Unit -10 to +85 C -55 to +150 C 1.0 W 100 mA -0.5 to VCCQ + 0.3 V -0.5 to 5.5 V -0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. OPERATING RANGE Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V +10%, -5% 3.3V +10%, -5% 6 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SP6464 DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current GND - VIN - VCCQ(2) GND - VOUT - VCCQ, OE = VIH Com. Ind. Com. Ind. Test Conditions IOH = -4.0 mA IOL = 8 mA Min. 2.4 -- 2.0 -0.3 -2 -10 -2 -10 ISSI Max. -- 0.4 VCCQ + 0.3 0.8 2 10 2 10 Unit V V V V A A (R) CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 5 7 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.3V. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 317 3.3V ZO = 50 Output Buffer OUTPUT 30 pF 50 5 pF Including jig and scope 351 1.5V Figure 1 Figure 2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 7 IS61SP6464 POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol ICC Parameter AC Operating Supply Current Test Conditions Device Selected, All Inputs = VIL or VIH OE = VIH, Cycle Time * tKC min. Device Deselected, VCC = Max., All Inputs = VIH or VIL CLK Cycle Time * tKC min. Device Deselected, VCC = Max., VIN = VCC * 0.2V, or VIN - 0.2V CLK Cycle Time * tKC min. ZZ = VCCQ, CLK Running All Inputs - GND + 0.2V or * VCC - 0.2V Com. Ind. -133 Max. 280 -- -117 Max. 270 290 -100 Max. 250 270 -6 Max. 200 220 -7 Max. 170 190 ISSI -8 Max. 150 170 Unit mA (R) ISB1 Standby Current TTL Inputs Com. Ind. 70 -- 70 80 70 80 70 80 70 80 70 80 mA ISB2 Standby Current CMOS Inputs Com. Ind. 20 -- 20 30 20 30 20 30 20 30 20 30 mA IZZ Power-Down Mode Current Com. Ind. 20 -- 20 30 20 30 20 30 20 30 20 30 mA Notes: 1. The MODE pin has an internal pullup. ZZ pin has an internal pull-down. This pin may be a No Connect, tied to GND, or tied to VCCQ. 2. The MODE pin should be tied to Vcc or GND. It exhibits 10 A maximum leakage current when tied to - GND + 0.2V or * Vcc - 0.2V. 8 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SP6464 READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tKQ tKQX (1) (1,2) ISSI -133 MHz Min. Max. 7.5 3 3 -- 1.5 0 2 -- 0 0 -- 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 -- -- -- 5 -- -- 5 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -117 MHz Min. Max. 8.5 3.4 3.4 -- 1.5 0 2 -- 0 0 -- 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 -- -- -- 5 -- -- 5 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -100 MHz Min. Max. 10 4 4 -- 2.5 0 2 -- 0 0 2 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 -- -- -- 5 -- -- 5 5 -- -- 5 -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (R) Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time tKQLZ tOEQ tKQHZ(1,2) tOEQX tOELZ tAS tSS tWS tCES tAVS tAH tSH tWH tCEH tAVH (1) (1,2) tOEHZ(1,2) Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 9 IS61SP6464 READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tKQ tKQX (1) (1,2) ISSI -6 ns Min. Max. 12 4.5 4.5 -- 2.5 0 2 -- 0 0 2 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 -- -- -- 6 -- -- 5 5 -- -- 5 -- -- -- -- -- -- -- -- -- -- -7 ns Min. Max. 13 5 5 -- 3 0 2 -- 0 0 2 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 -- -- -- 7 -- -- 5 5 -- -- 5 -- -- -- -- -- -- -- -- -- -- -8 ns Min. Max. 15 6 6 -- 3 0 2 -- 0 0 2 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 -- -- -- 8 -- -- 6 5 -- -- 6 -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (R) Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time tKQLZ tOEQ tKQHZ(1,2) tOEQX tOELZ tAS tSS tWS tCES tAVS tAH tSH tWH tCEH tAVH (1) (1,2) tOEHZ(1,2) Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 10 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SP6464 READ CYCLE TIMING tKC ISSI tSH tKH tKL (R) CLK tSS ADSP is blocked by CE inactive ADSP tSS tSH ADSC initiate read ADSC tAVS tAVH Suspend Burst ADV tAS tAH A15-A0 RD1 tWS tWH RD2 RD3 GW tWS tWH BWE BW8-BW1 tCES tCEH CE Masks ADSP CE tCES tCEH CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC Unselected with CE2, CE3 CE2, CE3 tCES tCEH CE2, CE3 tOEQ tOEHZ OE tOELZ tOEQX tKQX DATAOUT High-Z tKQLZ tKQ 1a 2a 2b 2c 2d 3a tKQHZ DATAIN High-Z Pipelined Read Single Read Burst Read Unselected Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 11 IS61SP6464 WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tAS tSS tWS tDS tCES tAVS tAH tSH tDH tWH tCEH tAVH Parameter Cycle Time Clock High Time Clock Low Time Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time -133 MHz Min. Max. 7.5 3 3 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -117 MHz Min. Max. 8.5 3.4 3.4 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ISSI -100 MHz Min. Max. 10 4 4 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (R) WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tAS tSS tWS tDS tCES tAVS tAH tSH tDH tWH tCEH tAVH Parameter Cycle Time Clock High Time Clock Low Time Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time -6 ns Min. Max. 12 4.5 4.5 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -7 ns Min. Max. 13 5 5 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -8 ns Min. Max. 15 6 6 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SP6464 WRITE CYCLE TIMING tKC ISSI tSH tKH tKL (R) CLK tSS ADSP is blocked by CE inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS ADV tAS tAH tAVH A15-A0 WR1 tWS tWH WR2 WR3 GW tWS tWH BWE tWS tWH tWS tWH BW8-BW1 tCES tCEH WR1 WR2 CE Masks ADSP WR3 CE tCES tCEH CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC Unselected with CE2, CE3 CE2, CE3 tCES tCEH CE2, CE3 OE DATAOUT High-Z tDS tDH BW8-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d 3a DATAIN High-Z 1a Single Write Burst Write Write Unselected Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 13 IS61SP6464 READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tKQ tKQX (1) (1,2) ISSI -133 MHz Min. Max. 7.5 3 3 -- 1.5 0 1.5 -- 0 0 -- 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 -- -- -- 5 -- -- 7.5 5 -- -- -- -- -- -- -- -- -- -- -- -117 MHz Min. Max. 8.5 3.4 3.4 -- 1.5 0 1.5 -- 0 0 -- 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 -- -- -- 5 -- -- 8.5 5 -- -- -- -- -- -- -- -- -- -- -- -100 MHz Min. Max. 10 4. 4 -- 2.5 0 2 -- 0 0 2 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 -- -- -- 5 -- -- 5 5 -- -- 5 -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (R) Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time tKQLZ tOEQ tKQHZ(1,2) tOEQX tOELZ tAS tSS tWS tCES tAH tSH tWH tCEH (1) (1,2) tOEHZ(1,2) Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 14 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SP6464 READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tKQ tKQX (1) (1,2) ISSI -6 ns Min. Max. 12 4.5 4.5 -- 2.5 0 2 -- 0 0 2 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 -- -- -- 6 -- -- 5 5 -- -- 5 -- -- -- -- -- -- -- -- -7 ns Min. Max. 13 5 5 -- 3 0 2 -- 0 0 2 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 -- -- -- 7 -- -- 5 5 -- -- 5 -- -- -- -- -- -- -- -- -8 ns Min. Max. 15 6 6 -- 3 0 2 -- 0 0 2 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 -- -- -- 8 -- -- 6 5 -- -- 6 -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (R) Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time tKQLZ tOEQ tKQHZ(1,2) tOEQX tOELZ tAS tSS tWS tCES tAH tSH tWH tCEH (1) (1,2) tOEHZ(1,2) Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 15 IS61SP6464 READ/WRITE CYCLE TIMING tKC ISSI tSH tKH tKL (R) CLK tSS ADSP is blocked by CE inactive ADSP tSS tSH ADSC ADV tAS tAH A15-A0 RD1 tWS tWH WR1 RD2 RD3 GW tWS tWH BWE tWS tWH BW8-BW1 tCES tCEH WR1 CE Masks ADSP CE tCES tCEH CE2, CE3 and CE2, CE3 only sampled with ADSP or ADSC CE2, CE3 tCES tCEH Unselected with CE2, CE3 CE2, CE3 tOEQ tOEHZ OE tOELZ tOEQX tKQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ 2a 2b 2c 2d tKQHZ DATAIN High-Z tDS 1a tDH Single Read Single Write Burst Read Unselected 16 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SP6464 ISSI -133 MHz Min. Max. 7.5 3 3 -- 0 0 1.5 -- 0 0 -- 2.5 2.5 2.5 0.5 0.5 0.5 2 2 -- -- -- 5 -- -- 7.5 5 -- -- -- -- -- -- -- -- -- -- -- -117 MHz Min. Max. 8.5 3.4 3.4 -- -- 0 1.5 -- 0 0 -- 2.5 2.5 2.5 0.5 0.5 0.5 2 2 -- -- -- 5 -- -- 8.5 4 -- -- -- -- -- -- -- -- -- -- -- -100 MHz Min. Max. 10 4 4 -- 2.5 0 2 -- 0 0 2 2.5 2.5 2.5 0.5 0.5 0.5 2 2 -- -- -- 5 -- -- 5 5 -- -- 5 -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc (R) SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tKQ tKQX (3) (3,4) Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Chip Enable Hold Time ZZ Standby (1) tKQLZ tOEQ tKQHZ(3,4) tOEQX tOELZ tAS tSS tCES tAH tSH tCEH tZZS tZZREC (3) (3,4) tOEHZ(3,4) ZZ Recovery(2) Notes: 1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data retention is guaranteed when ZZ is asserted and clock remains active. 2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state. 3. Guaranteed but not 100% tested. This parameter is periodically sampled. 4. Tested with load in Figure 2. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 17 IS61SP6464 ISSI -6 ns Min. Max. 12 4.5 4.5 -- 2.5 0 2 -- 0 0 2 2.5 2.5 2.5 0.5 0.5 0.5 2 2 -- -- -- 6 -- -- 5 5 -- -- 5 -- -- -- -- -- -- -- -- -7 ns Min. Max. 13 5 5 -- 3 0 2 -- 0 0 2 2.5 2.5 2.5 0.5 0.5 0.5 2 2 -- -- -- 7 -- -- 5 5 -- -- 5 -- -- -- -- -- -- -- -- -8 ns Min. Max. 15 6 6 -- 3 0 2 -- 0 0 2 2.5 2.5 2.5 0.5 0.5 0.5 2 2 -- -- -- 8 -- -- 6 5 -- -- 6 -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc (R) SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tKQ tKQX (3) (3,4) Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Chip Enable Hold Time ZZ Standby (1) tKQLZ tOEQ tKQHZ(3,4) tOEQX tOELZ tAS tSS tCES tAH tSH tCEH tZZS tZZREC (3) (3,4) tOEHZ(3,4) ZZ Recovery(2) Notes: 1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data retention is guaranteed when ZZ is asserted and clock remains active. 2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state. 3. Guaranteed but not 100% tested. This parameter is periodically sampled. 4. Tested with load in Figure 2. 18 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SP6464 SNOOZE AND RECOVERY CYCLE TIMING tKC ISSI tSS tSH tKH tKL (R) CLK ADSP ADSC ADV tAS tAH A15-A0 RD1 RD2 GW BWE BW8-BW1 tCES tCEH CE tCES tCEH CE2, CE3 tCES tCEH CE2, CE3 tOEQ tOEHZ OE tOELZ tOEQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ DATAIN High-Z tZZS tZZREC ZZ Single Read Snooze with Data Retention Read 19 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 IS61SP6464 ORDERING INFORMATION Commercial Range: 0C to +70C Speed 133 117 100 83 75 66 Order Part Number IS61SP6464-133TQ IS61SP6464-133PQ IS61SP6464-117TQ IS61SP6464-117PQ IS61SP6464-100TQ IS61SP6464-100PQ IS61SP6464-6TQ IS61SP6464-6PQ IS61SP6464-7TQ IS61SP6464-7PQ IS61SP6464-8TQ IS61SP6464-8PQ Package TQFP PQFP TQFP PQFP TQFP PQFP TQFP PQFP TQFP PQFP TQFP PQFP ISSI (R) Industrial Range: -40C to +85C Speed 133 117 100 83 75 66 Order Part Number IS61SP6464-133TQI IS61SP6464-133PQI IS61SP6464-117TQI IS61SP6464-117PQI IS61SP6464-100TQI IS61SP6464-100PQI IS61SP6464-6TQI IS61SP6464-6PQI IS61SP6464-7TQI IS61SP6464-7PQI IS61SP6464-8TQI IS61SP6464-8PQI Package TQFP PQFP TQFP PQFP TQFP PQFP TQFP PQFP TQFP PQFP TQFP PQFP ISSI (R) Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com 20 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. A 04/17/01 |
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